Conventional reconfigurable logic fabrics rely on sequential arrangements of synchronous circuits embedded within the fabric. The presence of synchronous circuits arranged in sequence within the fabric limits the speed at which a logic fabric can perform logical operations. Each circuit in the sequence chain must wait at least one clock cycle to receive the results of the computation of the previous circuit in the chain. This delay limits the speed at which conventional reconfigurable logic fabrics can operate. The present inventors have recognized the need for reconfigurable logic fabrics capable of operating at faster speeds than can be obtained using conventional synchronous logic fabrics.
Configuring conventional reconfigurable logic fabrics to comprise specific hardware circuit implementations is accomplished using off-line electronic design automation (EDA) tools. These tools presume the presence of synchronous circuits in the reconfigurable fabric. The present inventors have recognized the need for a reconfigurable logic fabric that is not only capable of faster computational speeds, but is also amenable to design using available EDA design tools.